Semiconductor chips typically comprise the bulk of the components in an electronic system. These semiconductor chips are also often the hottest part of the electronic system, and failure of the system can often be traced back to thermal overload on the chips. As such, thermal management is a critical parameter of semiconductor chip design.
FIG. 1 is a schematic diagram illustrating an exemplary semiconductor chip 100. As illustrated, the semiconductor chip 100 comprises one or more semiconductor devices 102a–102n (hereinafter collectively referred to as “semiconductor devices 102”), such as transistors, resistors, capacitors, diodes and the like deposited upon a substrate 104 and coupled via a plurality of wires or interconnects 106a–106n (hereinafter collectively referred to as “interconnects 106”). These semiconductor devices 102 and interconnects 106 share power, thereby distributing a thermal gradient over the chip 100 that may range from 100 to 180 degrees Celsius in various regions of the chip 100.
It is particularly important, when designing semiconductor chips, to determine whether such thermal gradients are within the bounds of a chip's operational limits (e.g., to ensure that a chip constructed in accordance with a given design will not overheat and trigger a failure when deployed for use). Conventional methods for testing temperatures within a semiconductor chip involve inserting temperature sensors (e.g., thermometers, thermistors, diode structures and the like), at locations of interest within a “dummy” or test chip. However, because the locations where steep thermal gradients may occur in the actual chip are not typically known at the time of design, the value of information learned through this random method is limited (e.g., the steepest thermal gradients may be missed and unaccounted for).
Therefore, there is a need in the art for a method and apparatus for thermal testing of semiconductor chip designs.